A new technique to deal with simultaneous testing of delay and stuck-a
t faults in digital integrated circuits is proposed. It consists of se
nsitising a path in the digital circuit under test and then incorporat
ing it in a ring oscillator to test for delay and stuck-at faults in t
he path. This procedure should be exercised for all, or at least criti
cal, paths in the circuit. This test technique can be used along with
scan techniques or implemented as a complete built-in self-test soluti
on.