In this paper, we have designed nineteen systolic arrays for matrix mu
ltiplication under the frame work of the systolic synthesis method usi
ng regular iterative algorithm (RIA) representation. Then we define di
fferent systolic array performance measures in order to evaluate the s
ystolic designs. The performance of the designed systolic arrays is an
alysed in details and this allows the comparison among the different s
ystolic designs.