IONIZED PHYSICAL VAPOR-DEPOSITION OF INTEGRATED-CIRCUIT INTERCONNECTS

Interconnects, once the technological backwater of integrated circuit technology, now dominate integrated circuit cost and performance. As m uch as 90 percent of the signal delay time in future integrated circui t designs will be due to the interconnection of semiconductor devices while the remaining 10 percent is due to transistor-related delay. Thi s shifts the thrust of critical research toward an improved understand ing of interconnect science and technology. Shrinking circuit geometri es will require high aspect ratio (AR) vias to interconnect adjacent m etal layers. By the year 2007 it is predicted that logic circuits will use 6 to 7 interconnected metal layers with via ARs of 5.2:1. Memory will need fewer layers, but ARs as high as 9:1. In this paper, the dem ands of interconnect technology will be reviewed and the opportunities for plasma-based deposition of vias will be discussed. One promising new method of fabricating high-aspect ratio vias is ionized physical v apor deposition (I-PVD). The technique economically creates a unidirec tional flux of metal which is uniform over 200-300 mm diameter wafers. Since metal ejected by conventional sputtering is primarily neutral a nd exhibits a cosine angular velocity distribution, sputtered metal at oms do not reach the bottom of high AR vias. By sputtering these atoms into a moderate pressure (4 Pa), high-density Ar plasma, however, the metal atoms are first thermalized and then ionized. The ions are then readily collimated by the plasma sheath and directionally deposited i nto narrow, deep via structures. Experiments have consistently shown t hat over 80% of the metal species are ionized using I-PVD. The physica l mechanisms responsible for ionization will be discussed from both an experimental and modeling perspective and the spatial variation of me tal ionization is experimentally determined. (C) 1998 American Institu te of Physics.