CHIP-SIZE PACKAGE TECHNOLOGY FOR SEMICONDUCTORS

Chip-scale packaging (CSP) of IC devices is rapidly gaining acceptance worldwide because of intrinsic size advantages, the promise of highly favorable cost/performance trade-offs and reliance on existing materi als and assembly infrastructures. The compliant, flex-circuit-based pa ckage is increasingly being viewed as the CSP method of choice. Flex-c ircuit-based, chip-sized packages that are not significantly larger th an the chip outline itself are available, enabling dense packaging of components and short interconnection distances, resulting in lower con ductance and reduced parasitics. Ball-grid array (BGA) CSP's are compa tible with most surface-mount assembly operations and have the testabi lity of a traditionally packaged die(1). These package design attribut es make the flex-based CSP an attractive die packaging solution for hi gh frequency applications as well as high speed digital devices. Activ ities are also underway to utilize the chip-size BGA package to interc onnect semiconductors at the wafer level where the totally integrated IC can be fabricated and tested in its final configuration while still on the wafer. This article reviews a novel chip-size BGA package cons truction, process flow and reliability data. Results of simulations an d measurements of high frequency signal characteristics on the package and through the interconnects are discussed, along with potential app lications for CSPs in the wireless industry.