PARALLEL ARCHITECTURE SUPPORT FOR HIGH-SPEED PROTOCOL PROCESSING

Authors
Citation
Ts. Chan et I. Gorton, PARALLEL ARCHITECTURE SUPPORT FOR HIGH-SPEED PROTOCOL PROCESSING, Microprocessors and microsystems, 20(6), 1997, pp. 325-339
Citations number
30
Categorie Soggetti
Computer Sciences","Engineering, Eletrical & Electronic","Computer Science Hardware & Architecture","Computer Science Theory & Methods
ISSN journal
01419331
Volume
20
Issue
6
Year of publication
1997
Pages
325 - 339
Database
ISI
SICI code
0141-9331(1997)20:6<325:PASFHP>2.0.ZU;2-7
Abstract
A rapid increase in the transmission bandwidth of optical networks has created a bottleneck in protocol processing at the host systems. This paper presents a high-performance transport protocol, HTPNET, that is designed to exploit the evolving characteristics of high-speed networ ks. Importantly, the highly parallel architecture of HTPNET provides a suitable platform for the parallel implementation of presentation pro cessing, which incurs high computation overheads. A parallel architect ure based on the T9000 transputer and C104 router technology has been designed to support high-speed protocol processing. A simulation of th e architecture has been implemented and has demonstrated the advantage of exploiting a parallel architecture for protocol processing.