GATE-OVERLAPPED LIGHTLY DOPED DRAIN POLY-SI THIN-FILM TRANSISTORS BY EMPLOYING LOW-TEMPERATURE DOPING TECHNIQUES

We have fabricated a gate-overlapped lightly doped drain (GO-LDD) poly crystalline silicon thin film transistor (poly-Si TFT) applicable for large area AMLCD by employing the large area-and low-temperature-dopin g techniques, such as ion shower doping and in-situ doping. Experiment al results show that the leakage current of the proposed TFTs is reduc ed by more than the magnitude of two orders, compared with that of con ventional non-offset TFT, while the ON current is scarcely decreased. The degradation phenomena after gate bias stress in GO-LDD TFTs with i n-situ doping has not been found because the electron trapping into th e overlayer may be suppressed effectively by the high quality TEOS int erlayer.