EVALUATION OF 0.3 MU-M POLYSILICON CMOS CIRCUITS FOR INTELLIGENT POWER IC APPLICATION

Citation
T. Matsudai et al., EVALUATION OF 0.3 MU-M POLYSILICON CMOS CIRCUITS FOR INTELLIGENT POWER IC APPLICATION, JPN J A P 1, 37(3B), 1998, pp. 1103-1106
Citations number
4
Categorie Soggetti
Physics, Applied
Volume
37
Issue
3B
Year of publication
1998
Pages
1103 - 1106
Database
ISI
SICI code
Abstract
In this paper, we report on The fine device performance of a 0.3 mu m gate length polysilicon complementary metaloxide-semiconductor (CMOS). The breakdown voltage of 0.3 mu m n-channel metal-oxide-semiconductor field effect transistor (NMOSFET) devices exceeds 6 V, which is highe r than that of NMOSFET devices on separation by implanted oxygen (SIMO X) wafer. The drain current of a 10 mu m channel width device is 540 m u A, which is one-fifth of that of NMOSFET on SIMOX. The leakage curre nt is less than 10(-11) A/mu m, when the gate voltage is below 0 V. Th e S-factor is 125 mV/dec, and the threshold voltage is 0.4 V. Therefor e the ON/OFF current ratio is greater than 10(7). A delay time of 1 ns is achieved in polysilicon NAND rings. Hence, it is ascertained that the polysilicon CMOS is applicable for the fabrication of control and protection circuits on power devices.