PARASITIC RESISTANCE CONSIDERATIONS OF USING ELEVATED SOURCE DRAIN TECHNOLOGY FOR DEEP-SUBMICRON METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS/

Device drive current, parasitic resistance, and junction leakage curre nt have been studied using silicided and non-silicided deep submicron elevated source/drain (ESD) n-channel metal oxide semiconductor field effect transistors (NMOSFETs). This study illustrated the effects of d oping profile in the elevated S/D region, junction depth in the substr ate, and doping level in the source/drain extension. Compared to devic es having nonelevated junctions with the same substrate doping profile , MOSFETs with a profile-doped elevated S/D, used to contact an ultras hallow junction formed before selective epitaxial growth, had higher d rive currents and demonstrated the ability of the elevated junction to reduce the extrinsic resistance. Measurements of drive currents in ES D devices showed that (i) the lightly doped region at the bottom of a profile-doped elevated layer introduces additional extrinsic resistanc e, and (ii) the locally deeper junction beneath the epi facets extends laterally toward the channel and shortens the drain extension length, thereby reducing the intrinsic resistance. Silicided devices had high er drive current and reduced parasitic resistance when the silicide/si licon interfacial dopant concentrations remained high (> 1 x 10(20)/cm (3)) after silicidation. The lowest total parasitic resistance was ach ieved when the elevated S/D was used to give a small contact resistanc e to a shallow junction and a moderately doped drain extension was use d to lower the resistance of the source/drain extension tab.