NONSCAN DESIGN-FOR-TESTABILITY TECHNIQUES USING RT-LEVEL DESIGN INFORMATION

Authors
Citation
S. Dey et M. Potkonjak, NONSCAN DESIGN-FOR-TESTABILITY TECHNIQUES USING RT-LEVEL DESIGN INFORMATION, IEEE transactions on computer-aided design of integrated circuits and systems, 16(12), 1997, pp. 1488-1506
Citations number
53
ISSN journal
02780070
Volume
16
Issue
12
Year of publication
1997
Pages
1488 - 1506
Database
ISI
SICI code
0278-0070(1997)16:12<1488:NDTURD>2.0.ZU;2-F
Abstract
This paper presents nonscan design-for-testability (DFT) techniques ap plicable to register-transfer (RT)-level data path circuits. Knowledge of high-level design information, in the form of the RT-level structu re, as well as the functions of the RT-level components is utilized to develop effective nonscan DFT techniques. Instead of conventional tec hniques of selecting hip-hops (FF's) to make controllable/observable, execution units (EXU's) are selected using the EXU S-graph introduced in this paper. Controllability/observability points can be implemented using register files and constants. We introduce the notion of k-leve l controllable and observable loops and demonstrate that it suffices t o make all the loops L-level controllable/observable, k > O, to achiev e very high test efficiency. The new testability measure eliminates th e need by traditional DFT techniques to make all loops directly (zero- level) controllable/observable, reducing significantly the hardware ov erhead required and making the nonscan DFT approach feasible and effec tive. We discuss ways of avoiding the formation of reconvergent region s while adding test points to make loops k-level controllable/observab le. We introduce dual points, which utilize the different controllabil ity/observability levels of loops, to make one loop controllable while making another loop observable. We present efficient algorithms to ad d the minimal hardware possible to make all loops in the data path k-l evel controllable/observable, without the use of scan PF's. The nonsca n DFT techniques were applied to several data path circuits. The exper imental results demonstrate the effectiveness of the L-level testabili ty measure, and the use of distributed and dual points, to generate ea sily testable data paths with reduced hardware overhead. The hardware overhead and the test application time required for the nonscan design s are significantly lower than for the partial scan designs. Most sign ificantly, the experimental results demonstrate the ability of the RT- level DFT techniques to produce nonscan testable data paths, which can be tested at-speed.