AN ANALYTICAL DELAY MODEL FOR RLC INTERCONNECTS

Elmore delay has been widely used to estimate interconnect delays in t he performance-driven synthesis and layout of very-large-seale-integra tion (VLSI) routing topologies. For typical RLC interconnections, howe ver, ELmore delay can deviate significantly from SPICE-computed delay, since it is independent of inductance of the interconnect and rise ti me of the input signal. Here, we develop an analytical delay model bas ed on first and second moments to incorporate inductance effects into the delay estimate for interconnection lines under step input. Delay e stimates using our analytical model are within 15% of SPICE-computed d elay across a wide range of interconnect parameter values. We also ext end our delay model for estimation of source-sink delays in arbitrary interconnect trees. We observe significant improvement in the accuracy of delay estimates for interconnect trees when compared to the Elmore model, yet our estimates are as easy to compute as ELmore delay. Eval uation of our analytical models is several orders of magnitude faster than simulation using SPICE. We also illustrate the application of our model in controlling response undershoot/overshoot and reducing inter connect delay through constraints on the moments.