Since the direct digital synthesizer (DDS) can potentially be used as
a flexible clock source, it is of interest to study ifs spectrum purit
y as well as jitter characteristic. In this paper, we investigate the
jitter transfer characteristic of the DDS clock driven by a jittered d
igital-to-analog converter (DAC) clock. We first derive the closed for
m expressions of the spectrum of the DAC output signal: with jittered
driving clock. These expressions are then used to investigate the spec
tral structure of the DDS clock, Equations are derived for the calcula
tion of the SNR. For a small phase noise power in the driving clock, t
he DDS clock SNR is obtained in a simple closed form and is shown to b
e lower than that of the input driving clock by the amount of 20 log(f
(s)/f(d)) dB, where f(s) is the nominal driving clock frequency and fd
is the desirable DDS output clock frequency.