DESIGN AND IMPLEMENTATION OF BANDPASS DELTA-SIGMA MODULATORS USING HALF-DELAY INTEGRATORS

Two bandpass delta-sigma AID converters using half-delay integrators h ave been designed and implemented in a 2-mu m n-well double-poly doubl e metal CMOS process. The first design, a fourth-order architecture wi th an input modulation network, achieves an signal-to-noise ratio (SNR ) of 73 dB over a 0.005 pi input bandwidth, while the second design, a sixth-order topology, yielded a measured SNR of 80 dB over a 0.004 pi input bandwidth.