A 160-MHZ 4TH-ORDER DOUBLE-SAMPLED SC BANDPASS SIGMA-DELTA MODULATOR

A fully differential double-sampled switched-capacitor (SC) architectu re for a fourth-order bandpass Sigma Delta modulator is presented. Thi s architecture is based on a double-sampled SC delay circuit. The effe ct of opamp nonidealities (finite de gain and nonzero input capacitanc e) on the notch frequency of this modulator is analyzed. The modulator is implemented in a 0.5-mu CMOS technology and operates at a clock fr equency of 80 MHz, making the effective sampling rate 160 MHz. The ima ge signal is about 40 dB below the fundamental signal, The measured si gnal-to-noise-plus;distortion (SNDR) is 47 dB (not including the image ) over a 1.25-MHz bandwidth centered at 40 MHz, The circuit operates a t 3 V and consumes 65 mW.