REPEATER DESIGN TO REDUCE DELAY AND POWER IN RESISTIVE INTERCONNECT

In large chips, the propagation delay of the data and clock signals ca n limit performance due to long resistive interconnect. The insertion of repeaters alleviates the quadratic increase in propagation delay wi th interconnect length while decreasing power dissipation by reducing short-circuit current. In order to develop a repeater design methodolo gy, a timing model characterizing a complementary metal-oxide-semicond uctor (CMOS) inverter driving a resistance-capacitance (RC) load is pr esented. The model is based on the Sakurai short-channel alpha-power l aw model of transistor operation. The inverter model is applied to the problem of repeaters to produce design expressions for determining th e optimum number of uniformly sized repeaters to be inserted along a r esistive interconnect line for reduced delay. For a wide variety of ty pical RC loads, this analytical repeater model exhibits a maximum erro r of 16% as compared to a dynamic circuit simulator (SPICE), The advan tage of uniformly sized repeaters versus tapered-buffer repeaters is a lso investigated using the repeater model presented in this paper. It is shown that uniform repeaters remain advantageous over tapered buffe rs and tapered-buffer repeaters even with relatively small resistive R C loads. An expression for the short-circuit power dissipation of a re peater driving an RC load is presented. A comparison of the short-circ uit power dissipation to the dynamic power dissipation in repeater cha ins and related power/delay tradeoffs are made.