LOW-POWER SWITCHED OUTPUT ADIABATIC LOGIC

A new adiabatic or energy recovery logic structure is presented in thi s circuit uses only one NMOS for precharge instead of two diodes as in previous circuits. Comparisons with previous circuits were carried ou t in terms of power dissipation, operating frequency and layout area. The results show that the proposed circuit can save around 20% of area in layout implementation with comparable power savings. The advantage s of the proposed circuit have been confirmed by HSPICE simulations an d layout design.