DESIGN METHODOLOGY FOR SYSTEMATIC DERIVATION OF FAULT-TOLERANT PROCESSOR ARRAY ARCHITECTURES

A systematic approach for mapping of iterative algorithms into fault-t olerant processor arrays is presented. The initial description of the algorithms is assumed to be Fortran-like nested loops, and it is not r equired to transform them into any intermediate form, such as UREs. Th e principles of Lamport's Coordinate Method are employed and regular o r piecewise, regular arrays (RA or PRA) can be derived. Moreover, the allocation and the scheduling of the computations are specified by sui table interpretation of the functional behaviour of each loop index. A lso, this paper proposes new approaches facilitating fault/defect-tole rant array processor design during the mapping process. An especially suited methodology is fault-tolerance via idle PEs.