ARCHITECTURE SCALABILITY OF PARALLEL VECTOR COMPUTERS WITH A SHARED-MEMORY

Based on a model of a parallel vector computer with a shared memory, i ts scalability properties are derived. The processor-memory interconne ction network is assumed to be composed of crossbar switches of size b x b. This paper analyzes sustainable peak performance under optimal c onditions, i.e., no memory bank conflicts, sufficient processor-memory bank pathways, and no interconnection network conflicts. It will be s hown that, with fully vectorizable algorithms and no communication ove rhead, the sustainable peak performance does not scale up linearly wit h the number of processors p, If the interconnection network is unbuff ered, the number of memory banks must increase at least with O(p log(b ) p) to sustain peak performance. If the network is buffered, this bot tleneck can be alleviated; however, the half performance vector length still increases with O(log(b) p). The paper confirms the validity of the model by examining the performance behavior of the LINPACK benchma rk.