A 200-MHZ COMPLEX NUMBER MULTIPLIER USING REDUNDANT BINARY ARITHMETIC

Modern digital communication systems rely heavily on baseband signal p rocessing for in-phase and quadrature (I-Q) channels, and complex numb er processing in low-voltage CMOS has become a necessity for channel e qualization, timing recovery, modulation, and demodulation, In this wo rk, redundant binary (RB) arithmetic is applied to complex number mult iplication for the first time so that an N-bit parallel complex number multiplier ran be reduced to two RE multiplications (i.e., an additio n of N RP partial products) corresponding to real and imaginary parts, respectively. This efficient RE encoding scheme proposed can generate RE partial products with no additional hardware and delay overheads. A prototype 8-bit complex number multiplier containing 11.5K transisto rs is integrated on 1.05 x 1.34 mm(2) using 0.8-mu m CMOS. The chip co nsumes 90 mW with 2.5-V supply when clocked at 200 MHz.