CYCLE SAVING HARDWARE FOR REAL-TIME AUDIO PROCESSING

The authors present a design for cycle saving hardware components that enable real-time operation of audio coder-decoders. To determine the key components of audio coding algorithms, the MPEG2 audio algorithm i s analysed, which is an international standard and uses a mixture of s everal coding strategies. Through the analysis, some components are se lected that significantly contribute to the total number of cycles, an d corresponding hardware accelerators that complete assigned tasks in a single cycle are designed. By incorporating these accelerators, a si mple processor can reduce the number of cycles for assigned tasks by u p to 72.2%.