A CHIP SET FOR PROGRAMMABLE REAL-TIME MPEG2 MP-AT-ML VIDEO ENCODER

This paper describes a chip set architecture and its implementation fo r programmable MPEG2 MP@ML (main profile at main level) video encoder. The chip set Features a functional partitioning architecture based on the MPEG2 layer structure. Using this partitioning scheme, an optimiz ed system configuration with double bus structure is proposed. In addi tion, a hybrid architecture with dual video-oriented on-chip RISC proc essors and dedicated hardware and a hierarchical pipeline scheme cover ing all layers are newly introduced to realize flexibility. Also, effe ctive motion estimation is achieved by a scalable solution for high pi cture quality. Adopting these Features, three kinds of VLSI have been developed using 0.5 micron double metal CMOS technology. The chip set consists of a controller-LSI (C-LSI), a macroblock level pixel process or-LSI (P-LSI) and a motion estimation-LSI (ME-LSI). The chip set comb ined with synchronous DRAMs (SDRAM) supports all the layer processing including rate-control and realizes real-time encoding for ITU-R-601 r esolution video (720 X 480 pixels at 30 frames/s) with glue less logic . The exhaustive motion estimation capability is scalable up to +/-63. 5 and +/-15.5 in the horizontal and vertical directions respectively. This chip set solution realizes a low cost MPEG2 video encoder system with excellent video quality on a single PC extension board. The evalu ation system and application development environment is also introduce d.