A VLSI ARCHITECTURE FOR MOTION ESTIMATION CORE DEDICATED TO H.263 VIDEO CODING

A VLSI architecture of a motion estimator is described dedicatedly for the H.263 low bitrate video coding. Adopting an efficient hierarchica l search algorithm, a new motion estimator yields high quality vectors with small area occupancy and at a low operation frequency. A one-dim ensional PE (Processing Element) array is devised to be tuned to the H .263 encoding, which treats both the advanced prediction mode and the PB-frame mode. The proposed motion estimation core is integrated in 1. 55 mm(2) by using 0.35 mu m CMOS 3LM technology, which operates at 15 MHz, and hence enables the realtime motion estimation of QCIF pictures .