DESIGN OF 1024-I OS 3.84 GB/S HIGH-BANDWIDTH 600 MW LOW-POWER 16 MB DRAM MACROS FOR PARALLEL IMAGE-PROCESSING RAM/

We have developed a parallel image processing RAM (PIP-RAM) which inte grates a 16-Mb DRAM and 128 processor elements (PEs) by means of 0.38- mu m CMOS 64-Mb DRAM process technology. It achieves 7.68-GIPS process ing performance and 3.84-GB/s memory bandwidth with only 1-W power dis sipation (@ 30-MHz),and the key to this performance is the DRAM design . This paper presents the key circuit techniques employed in the DRAM design: 1) a paged-segmentation accessing scheme that reduces sense am plifier power dissipation, and 2) a clocked low-voltage-swing differen tial-charge-transfer scheme that reduces data line power dissipation w ith the help of a multi-phase synchronization DRAM control scheme. The se techniques have general importance for the design of LSIs in which DRAMs and logic are tightly integrated on single chips.