POWER ESTIMATION METHOD FOR HIGHLY CORRELATED INPUT SEQUENCES UNDER REALISTIC DELAY MODEL

Citation
H. Kim et al., POWER ESTIMATION METHOD FOR HIGHLY CORRELATED INPUT SEQUENCES UNDER REALISTIC DELAY MODEL, Electronics Letters, 34(10), 1998, pp. 937-939
Citations number
4
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
ISSN journal
00135194
Volume
34
Issue
10
Year of publication
1998
Pages
937 - 939
Database
ISI
SICI code
0013-5194(1998)34:10<937:PEMFHC>2.0.ZU;2-C
Abstract
A new power estimation method is presented which considers spatio-temp oral correlations among the primary inputs as well as the glitch effec t under a realistic delay model. To deal with the glitch effect, the s ymbolic simulation technique is employed, and to take the correlations among the primary inputs into account, the authors employ a new techn ique which transforms correlation information into a logic structure, called 'pre-logic.' Experimental results show that the estimation erro r of the proposed method is similar to 4% under a realistic delay mode l with highly correlated input streams.