Ion implant manufacturers face process-and productivity-driven equipme
nt performance challenges as device design rules shrink into the less
than or equal to 0.18-mu m regime and wafer size moves from 200 to 300
mm. These challenges apply to all three implanter segments (high curr
ent, medium current, and high energy) and can be separated into two di
stinct categories: process-level and productivity-level challenges. Ap
proaches to these challenges vary among ion implant equipment manufact
urers. Several key process-and productivity-level challenges will have
the greatest effect on Mure equipment designs. These are the formatio
n of ultrashallow junctions in the sub-100-nm range in production envi
ronments (high-current implanters); the cost-effective formation of hi
gh-dose, high-energy buried layers (high-energy implanters); and the p
recision placement of dopants in sub-0.25-mu m channels (medium-curren
t implanters).