Multiple-output multilevel logic circuits synthesis technique using multiplexers

In this paper a new efficient synthesis technique for multiple-output multi level combinational logic circuits is described. For an implementation of l ogic circuits the use of universal logic modules - multiplexers - is assume d. A reduced canonical multiplexer tree is the basis for circuits structure . The decomposition of collection m functions of n variables and the reduct ion of canonical multiplexer trees are made by means of the table of residu e functions. The resulting circuits are well suited for FPGA's implementati ons. The synthesis technique presented has been implemented in TURBO C++ on PC under MS-DOS. The computer program creates such tree structure, which c ontains a minimum number of logic levels and multiplexers.