A 1-Gb/s bidirectional I/O buffer using the current-mode scheme

A current-mode bidirectional I/O buffer was designed, and the maximum effec tive bandwidth of 1.0 Gb/s per wire was obtained from measurements. To enha nce the operating speed, the voltage swing on the transmission line was red uced to 0.5 V and the internal nodes of the buffer were designed to be low impedance nodes using the current-mode scheme. An automatic impedance-match ing scheme was used to generate bias voltages, which adjust output resistan ce of the buffer to be equal to the characteristic impedance of the transmi ssion line in spite of process variations. The chip was fabricated by using a 0.8-mu m CMOS technology. The chip size was 500 x 330 mu m(2), and the p ower consumption was 50 mW at a supply voltage of 3 V.