An IC containing four clock deskew buffers using the delay-locked-loop tech
nology has been fabricated in a 0.6-mu m single poly double metal CMOS proc
ess. The core chip area is 0.9 x 0.9 mm(2), The maximum operating frequency
is 80 MHz, and the total power dissipation of the four deskew buffers is 5
9 mW for a 3-V supply voltage, The maximum clock skew after deskewing is le
ss than 300 ps, and the peak-to-peak clock jitter is less than 170 ps. The
deskew range is 0.5-3.8 ns.