Fully depleted CMOS/SOI device design guidelines for low-power applications

We report the fully depleted (FD) CMOS/SOI device design guidelines for low -power applications. Optimal technology, device and circuit parameters are derived and compared with bulk CMOS based design. The differences and simil arities are summarized, Del ice design guidelines using devices with L = 0. 1 mu m for FDSOI low-power applications are presented using an empirical dr ain saturation current model fitted to experimental data. The model is veri fied in the deep-submicron regime by two-dimensional (2-D) simulation. For L = 0.1 mu m FDSOI low-power technology, optimum speed and lower-power occu rs at V-dd = 3V(th), and V-dd = 1.5V(th), respectively. Optimum buried oxid e thickness is found to be between 300 and 400 nm for low-power application s. Optimum transistor sizing is when the driver device capacitance is 0.3 t imes the total load capacitance. Similarly optimum gate oxide thickness is when the driver device gate capacitance is 0.2-0.6 times the total load cap acitance for performance and 0.1-0.2 for low-power, respectively. Finally o ptimum stage ratio for driving large loads is around 2-4 for both high-perf ormance and low-power.