0.21-fJ GaAs DCFL circuits using 0.2-mu m Y-shaped gate AlGaAs/InGaAs E/D-HJFETs

Ultra-low-power-consumption and high-speed DCFL circuits have been fabricat ed by using 0.2-mu m Y-shaped gate E/D-heterojunction-FETs (HJFETs) with a high-aspect-ratio gate-structure, which has an advantage of reducing the ga te-fringing capacitance (C-f) to about a half of that of a conventional low -aspect-ratio one. A fabricated 51-stage ring oscillator with the 0.2-mu m Y-shaped gate n-A1GaAs/i-InGaAs E/D-HJFETs shows the lowest power-delay pro duct of 0.21 fJ with an unloaded propagation delay of 34.9 ps at a supply v oltage (V-DD) of 0.4V. We also analyze the DCFL switching characteristics b y taking into account the intrinsic gate-to-source capacitance (C-gs(int)) and the C-f. The analysis results for the power-delay products agree well w ith our experimental results. Our analysis also indicates the DCFL circuit with the high-aspect-ratio Y-shaped gate E/D-HJFETs can reduce the power-de lay products by 35% or more below 0.25-mu m gate-length as compared to conv entional ones with the low-aspect-ratio Y-shaped gate HJFETs. These results clarify that the C-f-reduction of the Y-shaped gate HJFETs is more effecti ve in improving the power-delay products than reducing the gate-length.