Low-power 2.5-Gb/s Si-bipolar IC chipset for optical receivers and transmitters using low-voltage and adjustment-free circuit techniques

This paper describes a 2.5-Gb/s optical receiver and transmitter chipset co nsisting of a preamplifier, a main amplifier, a clock and data recovery (CD R) circuit, and a laser-diode (LD) driver. Low-voltage and adjustment-free circuit techniques are introduced in order to achieve low cost and low powe r circuits. Circuit adjustments are eliminated by using a multi-stage autom atic offset canceling technique in the main amplifier, and by using a PLL s tructure with a sample-and-hold technique in the CDR circuit. For power red uction, ICs are operated at a power supply voltage of -3 V. Fabricating the ICs by a 0.5-mu m Si bipolar process makes it possible to achieve 2.5-Gb/s receiver and transmitter operation with a total power dissipation of 1.04 W. Especially significant is that the receiver ICs need no external devices and adjustments.