A depth-constrained technology mapping algorithm for logic-blocks composedof tree-structured LUTs

This paper proposes a fast depth-constrained technology mapping algorithm f or logic-blocks composed of tree-structured lookup tables. First, we propos e a technology mapping algorithm which minimizes the number of logic-blocks if an input Boolean network is a tree. Second, we propose a technology map ping algorithm which minimizes logic depth for any input Boolean network. F inally, we combine those two technology mapping algorithms and propose an a lgorithm which realizes technology mapping whose depth is bounded by a give n upper bound d(c). Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.