A functional-level testability measure for register-level circuits and itsestimation

Estimation of circuit testability is an important issue when evaluating the circuit design. A testability measure indicates how easy or difficult it w ould be to generate tests for the circuit. STAFAN (Statistical Fault Analys is) is a well known gate-level testability analysis program which predicts the fault coverage of a digital circuit under the stuck-at fault model, wit hout actually performing fault simulation. STAFAN offers speed advantage ov er other testability analysis programs such as SCOAP; further, it explicitl y predicts the fault coverage for a given test set, unlike other testabilit y measures which are harder to interpret. We show how a STAFAN-like testabi lity analysis program can be constructed for circuits built out of register -level modules such as adders, multipliers, multiplexers, and busses. Our t ool, which we call FSTAFAN, is useful in a testability-driven high-level sy nthesis environment. We have implemented FSTAFAN on a Sun/SPARC workstation and describe its performance on some register-level circuits. (C) 1999 Els evier Science B.V. All rights reserved.