The design and performance characteristics of a 16-channel Winner-Sele
ct-Output (WSO) ASIC are presented. The WSO ASIC does a fast compariso
n of 16 analog input voltages, outputs the maximum signal, the ''secon
d'' maximum (partner) signal, and their addresses. The WSO ASIC chip i
s a key component of an analog electronics system being developed for
a depth of interaction (DOT) PET detector module. The basic cell of th
e WSO ASIC is a ''winner take all'' (WTA) circuit. The precision of th
e WSO ASIC is enhanced by using a cascade structure WTA cell. The chip
requires a single +5V supply and consumes 35 mW of power. The WSO ASI
C is sensitive to voltage differences as small as 10 mV. The propagati
on delay of the chip is less than 30 nsec for voltage differences of >
50 mV (typical for proposed application).