FAIR - A NEW FAST TRIGGER AND READOUT BUS SYSTEM

FAIR (FAst Intercrate Readout) is a synchronous ECL bus system dedicat ed to readout. It is based on a new trigger and readout hardware level protocol and an on a new control system that ''learns'' how to setup and control modules. The hardware protocol along with the data structu re allow both readout and event building at the same time at the rate of 22 ns/longword (1.44 Gbit/s) without the need of CPUs. It performs trigger management and full pipelining by using a multilevel FIFO stru cture. FAIR provides for a multi-crate front-end environment and uses an embedded serial network to accomplish front-end control and setup. The data transfer measured performances and the control system are pre sented in some detail.