LATENT INTERFACE-TRAP GENERATION IN COMMERCIAL POWER VDMOSFETS

Latent interface-trap generation is one of the most controversial post -irradiation effects in MOSFETs, which can have a significant impact o n device performance and reliability in radiation environments. In thi s paper, we present new experimental evidence of latent interface-trap buildup in commercial power VDMOSFETs: its dependencies on dose, temp erature and gate bias applied during irradiation and annealing. We dis cuss several models for latent interface-trap buildup and show that th e most consistent is one which involves the diffusion of molecular hyd rogen from structures adjacent to the gate oxide (CVD oxide, poly-Si S ate), and its cracking on positive charge centers in the oxide. The cr acking reaction liberates hydrogen ions, which drift to the Si/SiO2 in terface to form interface traps. Some hypothesis from the recently pro posed H-W model for post-irradiation behavior of interface traps may h elp resolve the question of the source of hydrogen sufficient to cause up to 800% increase in interface-trap density, experimentally observe d. The implications of latent interface-trap generation for hardness a ssurance test methods are also discussed.