A METHODOLOGY TO STUDY LATERAL PARASITIC TRANSISTORS IN CMOS TECHNOLOGIES

This work concerns the development of a methodology specially devoted to lateral parasitic transistors that limit the total dose hardness of CMOS technologies. This methodology is based on i) the irradiation of standard NMOS transistors followed by ii) isochronal annealing measur ements to determine energetic spectra of the field oxide trapped charg e. Post irradiation effects have been evaluated through additional iso thermal annealing experiments at 75 degrees C which are consistent wit h isochronal results. We propose a test procedure which allows to dete rmine physical parameters helpful to improve comparison and qualificat ion of CMOS commercial technologies.