A NEW INTEGRATED TEST STRUCTURE FOR ON-CHIP POSTIRRADIATION ANNEALINGIN MOS DEVICES

Authors
CHABRERIE C AUTRAN JL FLAMENT O BOUDENOT JC
Citation
C. Chabrerie et al., A NEW INTEGRATED TEST STRUCTURE FOR ON-CHIP POSTIRRADIATION ANNEALINGIN MOS DEVICES, IEEE transactions on nuclear science, 45(3), 1998, pp. 1438-1443
Citations number
8
Categorie Soggetti
Nuclear Sciences & Tecnology","Engineering, Eletrical & Electronic
Journal title
IEEE transactions on nuclear science → ACNP
ISSN journal
00189499
Volume
45
Issue
3
Year of publication
1998
Part
3
Pages
1438 - 1443
Database
ISI
SICI code
0018-9499(1998)45:3<1438:ANITSF>2.0.ZU;2-9
Abstract
We have developed a prototype test structure (named THERMOS) demonstra ting the feasibility and the interest of the on-chip heating in a Sili con-On-Insulator technology. This circuit has been specially designed for the study of post-irradiation effects in a radiation-hardened CMOS technology. Preliminary results are presented here for the on-chip an nealing of irradiated n-channel transistors.