ATLAS-I - A SINGLE-CHIP, GIGABIT ATM SWITCH WITH HIC HS LINKS AND MULTILANE BACK-PRESSURE/

ATLAS I is a single-chip ATM switch that uses IEEE Std. 1355 'HIC' gig abit links and implements optional credit-based flow control. It is a 16 x 16 switch with 20 Gb s(-1) aggregate I/O throughput, three priori ty levels, 256-cell shared buffer, and 54 output queues achieving subm icrosecond cut-through latency; furthermore, it supports rate-based fl ow control, link bundling, multicasting, and load monitoring. ATLAS I is targeted at use in interconnections ranging from wide area (WAN) to LAN and desktop (DAN) networking, and supports a mixture of services from real-time, guaranteed quality-of-service to best-effort, bursty a md flooding traffic. Target applications range from telecom to multime dia and multiprocessor NOWs. ATLAS I implements a multi-lane back-pres sure (credit) flow control scheme, which in conjunction with shared bu ffering provides high performance and robust operation, since it elimi nates the head-of-line blocking problems of input queuing and single-l ane back-pressure. We present the queue model of the switch, we descri be how multi-lane back-pressure is added on top of single-lane 1355 st andard links, as an optional extension, and we show how the link inter faces are implemented and how their parameters are evaluated. (C) 1998 Elsevier Science B.V.