HIGH-FREQUENCY PERFORMANCES OF A PARTIALLY DEPLETED 0.18-MU-M SOI CMOS TECHNOLOGY AT LOW SUPPLY VOLTAGE - INFLUENCE OF PARASITIC ELEMENTS/

This paper shows for the first time the high-frequency performances of a partially depleted 0.18-mu m SOI/CMOS technology at low supply volt age. The SOI technology uses a standard digital process with a TiSi2 s alicided polysilicon gate and a low dose SIMOX substrate. The process does not include any specific feature like T-gate, or high-resistivity SOI substrate. At 1 V, and 2 GHz the current gain and the unilateral power gain are higher than 15 dB for both 0.18 mu m gate length NMOS a nd PMOS transistors. At 1.5 V, the 0.18-mu m NMOS and PMOS show a tran sition frequency of, respectively, 51 GHz and 23 GHz and a maximum osc illation frequency of 28 GHz and 13 GHz. These results have been obtai ned with an optimized transistor geometry to reduce the influence of t he access resistances. The high-frequency potential of this 0.18-mu m SOI technology demonstrates the possible integration of microwave func tions with digital circuits on a single chip for low-power, low-voltag e applications like wireless telecommunication.