THE IMPACT OF SCALING DOWN TO DEEP-SUBMICRON ON CMOS RF CIRCUITS

Recent papers reporting CMOS RF building blocks have aroused great exp ectations for RF receivers using deep-submicron technologies. This pap er examines the trend in CMOS scaling, in order to establish the requi red current levels and achievable performance for different feature si zes, if robust, easily manufacturable designs are to be implemented fo r cellular applications, The boundary conditions (system-level constra ints) for such designs, in terms of the number of trimmed and untrimme d external components and the roles they play in relaxing active circu it requirements, are emphasized throughout to make comparison of activ e RF circuits meaningful. At 1 GHz, 0.25-mu m CMOS appears to be the t hreshold for robust, low-NF RF front ends with current consumption com petitive with today's BJT implementations.