NOVEL LEVEL-IDENTIFYING CIRCUIT FOR FLASH MULTILEVEL MEMORIES

This paper presents a high-speed, small-area circuit specifically desi gned to identify the levels in the read-out operation of a Flash multi level memory. The circuit is based on the analog computation of the Eu clidean distance between the current read out from a memory cell and t he reference currents that represent the different logic levels. An ex perimental version of the circuit has been integrated in a standard do uble-metal 0.7-mu m CMOS process with a die area of only 140 x 100 mu m(2). Operating under a 5-V power supply, this circuit identifies the read-out current of a memory cell, and associates it with the appropri ate logic level in 9 ns.