A LOW-NOISE FOLDED BIT-LINE SENSING ARCHITECTURE FOR MULTIGIGABIT DRAM WITH ULTRAHIGH-DENSITY 6F(2) CELL

The 6F(2) cell is widely known for its small area, but its sensing is unstable due to the large array noises. A new low-noise sensing scheme for a 6F(2) DRAM cell is proposed, employing two noise reduction meth ods: the divided sense and combined restore scheme and the bit-line no ise absorbing scheme. They can reduce word-line to bit-line as well as bit-line to bit-line coupling noises, The bit-line noise is reduced t o 85% of that of a conventional scheme,vith only 0.05% area overhead, which is negligible compared to the area saving by using a 6F(2) cell. The total chip area and the sensing time can be reduced to 85 and 87% , respectively, compared to conventional DRAM, A 2 kbit DRAM test chip with a 6F(2) cell is fabricated using 256 M DRAM technology, and its stable operations are confirmed.