LOW-POWER 200-MSPS, AREA-EFFICIENT, 5-TAP PROGRAMMABLE FIR FILTER

Authors
MOLONEY D OBRIEN J OROURKE E BRIANTI F
Citation
D. Moloney et al., LOW-POWER 200-MSPS, AREA-EFFICIENT, 5-TAP PROGRAMMABLE FIR FILTER, IEEE journal of solid-state circuits, 33(7), 1998, pp. 1134-1138
Citations number
13
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
IEEE journal of solid-state circuits → ACNP
ISSN journal
00189200
Volume
33
Issue
7
Year of publication
1998
Pages
1134 - 1138
Database
ISI
SICI code
0018-9200(1998)33:7<1134:L2A5PF>2.0.ZU;2-3
Abstract
A two-sample per cycle, programmable five-tap, area-efficient finite-i mpulse response (FLR) filter for hard-disk drive PRML read channels is presented. The design is optimized for low power, achieving a figure of 6.25 mu W/MHz [6] with a gate density of 2.3 K, by a combination of algorithmic, architectural, circuit-level, and layout techniques.