LOGIC DESIGN OF A FAST CIRCUIT FOR ITERATIVE ADDITIONS IN REDUNDANT HYBRID NUMBER-SYSTEMS

Authors
ALIA G MARTINELLI E
Citation
G. Alia et E. Martinelli, LOGIC DESIGN OF A FAST CIRCUIT FOR ITERATIVE ADDITIONS IN REDUNDANT HYBRID NUMBER-SYSTEMS, Computer journal (Print), 41(1), 1998, pp. 45-51
Citations number
19
Categorie Soggetti
Computer Science Hardware & Architecture","Computer Science Information Systems","Computer Science Software Graphycs Programming","Computer Science Hardware & Architecture","Computer Science Information Systems","Computer Science Software Graphycs Programming
Journal title
Computer journal (Print) → ACNP
ISSN journal
00104620
Volume
41
Issue
1
Year of publication
1998
Pages
45 - 51
Database
ISI
SICI code
0010-4620(1998)41:1<45:LDOAFC>2.0.ZU;2-J
Abstract
Repeated modular additions and overflow detection are possible in redu ndant hybrid number systems (RHNS). In this paper a circuit is propose d that implements the overflow-detecting procedure in such systems and allows a mean addition time of about 10.5 gate delays for numbers hav ing a magnitude order normally distributed in the range [-2(33), 2(33) - 1]versus a 14 gate delay required by 32-bit CLA adders.