DESIGN OF A K-BAND POWER-AMPLIFIER USING ON-WAFER-TUNING LOAD-PULL METHOD

Citation
M. Ida et M. Nakatsugawa, DESIGN OF A K-BAND POWER-AMPLIFIER USING ON-WAFER-TUNING LOAD-PULL METHOD, IEICE transactions on electronics, E81C(6), 1998, pp. 882-885
Citations number
2
Categorie Soggetti
Engineering, Eletrical & Electronic
ISSN journal
09168524
Volume
E81C
Issue
6
Year of publication
1998
Pages
882 - 885
Database
ISI
SICI code
0916-8524(1998)E81C:6<882:DOAKPU>2.0.ZU;2-P
Abstract
In high-frequency operation, it is difficult to obtain a large tuning range in lend-pull measurement due to losses in the tuning network and RF-probes. In this paper, a low-loss on-wafer-tuning load-pull method is proposed. The output matching network consists of two CPWs connect ed to a FET output terminal. The impedance of the network can be contr olled by changing the effective length of the CPWs by replacing RF-pro bes and removing air-bridges. To confirm the validity of this load-pul l method, a K-band high-efficiency MMIC power amplifier has been desig ned using the method and fabricated. The amplifier demonstrates perfor mance of 19.5-dBm saturated output power, 12.5-dB linear gain and 49.3 % maximum power-added efficiency (PAE) at V-ds = 3 V for 26 GHz operat ion. Atl-dB gain-compression, the PAE is still as high as 44%; This hi gh PAE result clearly indicates that the proposed method is a useful t ool for designing power amplifiers, especially those for use in high-f requency (e.g. K-band) operation.