A SIMULATION METHODOLOGY FOR BIDIRECTIONAL HOT-CARRIER DEGRADATION INA STATIC RAM CIRCUIT

A simulation methodology to analyze hot-carrier degradation due to bid irectional stressing in a static RAM circuit has been developed. The b idirectional stressing of pass transistors can approximate to unidirec tional stressing. The effective stress direction of each NMOSFET can b e determined by the higher of the two junction voltages at the peak su bstrate current generation. Aged SPICE parameter sets extracted in the forward or in the reverse mode are selected for simulating the degrad ation of each NMOSFET. Furthermore, effects of each NMOSFET degradatio n on the degraded circuit behavior are simulated. This technique helps detect an NMOSFET having the largest influence on the circuit aging, improving circuit reliability. The methodology was successfully applie d to an SRAM device, and was validated by low temperature bias test da ta.