ANALYTIC MODELING OF UPDATING BASED CACHE COHERENT PARALLEL COMPUTERS

In this paper, we apply the Semi-markov Memory and Cache coherence Int erference (SMCI) model, which we had proposed for invalidating based c ache coherent parallel computers, to an updating based protocol. The m odel proposed here, the SMCI/Dragon model, can predict performance of cache coherent parallel computers with the Dragon protocol as well as the original SMCI model for the Synapse protocol. Conventional analyti c models by stochastic processes to describe parallel computers have t he problem of numerical explosion in the number of states necessary as the system size increases. We have already shown that the SMCI model achieved both the small number of states to describe parallel computer s with the Synapse protocol and the inexpensive computation cost to pr edict their performance. In this paper, we demonstrate generality of t he SMCI model by applying it to the another cache coherence protocol, Dragon, which has opposite characteristics than Synapse. We show the n umber of states required by constructing the SMCI/Dragon model is only 21 which is as small as SMCI/Synapse, and the computation cost is als o the order of microseconds. Using the SMCI/Dragon model, we investiga te several comparative experiments with widely known simulation result s. We found that there is only a 5.4% differences between the simulati on and the SMCI/Dragon model.