PARALLEL ARCHITECTURE FOR GENERALIZED LFSR IN LSI BUILT-IN SELF-TESTING

This paper presents a new architecture for multiple-input signature an alyzers. The proposed signature analyzer with H delta inputs is design ed by parallelizing a GLFSR(delta, m), where delta is the number of in put signals and m is the number of stages in the feedback shift regist er. The GLFSR, developed by Pradhan and Gupta, is a general framework for representing LFSR-based signature analyzers. The parallelization t echnique described in this paper can be applied to any kind of GLFSR s ignature analyzer, e.g., SISRs, MISRs, multiple MISRs and MLFSRs. It i s shown that a proposed signature analyzer with H delta inputs require s less complex hardware than either single GLFSR(H delta, m)s or a par allel construction of the H original GLFSR(delta, m)s. It is also show n that the proposed signature analyzer, while requiring simpler hardwa re, has comparable aliasing probability with analyzers using conventio nal GLFSRs for some CUT error models of the same test response length and test lime. The proposed technique would be practical for testing C UTs with a large number of output sequences, since the test circuit oc cupies a smaller area on the LSI chip than the conventional multiple-i nput signature analyzers of comparable aliasing probability.