PROCESS TECHNOLOGY AND INTEGRATION CHALLENGES FOR HIGH-PERFORMANCE INTERCONNECTS

Interconnect metallization for 0.18 mu m technology presents many new challenges for the process technologies. The DRAM device architecture imposes severe requirements of shallow junctions and narrow line width s, which combine to put constraints on the thermal budget while requir ing low RC time constant for the interconnects. A number of new materi als, such as TiSix, TiN, W, WN, Pt, and Ru are under consideration for interconnect and capacitor plate metallization. These materials need to provide low resistance lines, be thermally stable, and have no dele terious effects on the gate oxide and capacitor dielectric, and they m ust be compatible with the overall process flow. Deposition processes for interconnect materials as well as interlevel dielectrics with supe rior conformality are necessary for a complete fill without voids. A r eview of the requirements for a manufacturable interconnect scheme and the limitations of the current technology is presented. (C) 1998 Else vier Science S.A. All rights reserved.