Tungsten plugs have been used in the recent past for local interconnec
ts and for level-level interconnect applications. The resist etch back
process has been the method of choice historically for planarization
purposes. However, with the advent of chemical mechanical polishing (C
MP) technology, one has an alternate path for achieving global planari
ty. Process integration issues have to be worked out. In this paper, w
e have explored the effect of various process parameters and consumabl
e changes on planarity/non-uniformity. The across wafer and wafer-wafe
r non-uniformity 1-sigma was reduced from 10-20% to < 10%. The optimiz
ed process was verified on a 500 wafer extended run to obtain > 5000 A
ngstrom/min with 5.5% wafer-wafer removal variation. (C) 1998 Elsevier
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